After generate a R-tile scalable switch ip example for AGIB027R29A1E2VR3 with quartus25.1 ,there is no testbench.how to do simuation?

Hi,Which simulator that you try to use ?You may find the simulation folder under ../xxx../switchIP/intel_pcie_sep_rtile_top_0_example_design/switch_ed/sim/Please ensure that you enable the simulation tab upon design example generationLet me know if you still unable to find it.Regards,Wincent_Altera

There is only a sim top file under switch_ed/sim directory,no testbench file.can you snapshot?

Hi Wilson,If you are refer to the xxx_tb.v file you can refer to switch_ed.vLet me know if I am not answering your question or I miss-understand anything.Regards,Wincent_Altera

There are two demux_1stage_pipeline code under switch_user_logic/demux.v .The upper parts are commented.The lower parts are opened.I want to use the upper parts code(commented). can it work?// --------------------------------------------------------------------------------// | single buffered pipeline stage// --------------------------------------------------------------------------------//module demux_1stage_pipeline// #( parameter PAYLOAD_WIDTH = 8 )// ( input clk,// input reset_n,// output reg in_ready,// input in_valid,// input [PAYLOAD_WIDTH-1:0] in_payload,// input out_ready,// output reg out_valid,// output reg [PAYLOAD_WIDTH-1:0] out_payload// );//// reg in_ready1;// always @* begin// in_ready = out_ready || ~out_valid;// // in_ready = in_ready1;// // if (!out_ready)// // in_ready = 0;// end//// always @ (posedge clk) begin// if (!reset_n) begin// in_ready1 <= 0;// out_valid <= 0;// out_payload <= 0;// end else begin// in_ready1 <= out_ready || !out_valid;// if (in_valid) begin// out_valid <= 1;// end else if (out_ready) begin// out_valid <= 0;// end// if(in_valid && in_ready) begin// out_payload <= in_payload;// end// end // else: !if(!reset_n)// end // always @ (negedge reset_n, posedge clk)//endmodule //module demux_1stage_pipeline#( parameter PAYLOAD_WIDTH = 8 )( input clk,input reset_n,output reg in_ready,input in_valid,input [PAYLOAD_WIDTH-1:0] in_payload,input out_ready,output reg out_valid,output reg [PAYLOAD_WIDTH-1:0] out_payload);always @ (posedge clk or negedge reset_n)beginif (!reset_n)beginout_valid <= 0;out_payload <= 0;in_ready <= 0;endelsebeginin_ready <= out_ready;out_valid <= in_valid;out_payload <= in_payload;endendendmodule//

Hi Wilson,Is there any special reason you need to used the commended part ?Just try to understand more and check if the application is ideal or not.I want to use the upper parts code(commented). can it work?>> Well, as I go through the code, the (commented) code seen to be likely more robust in handling backpressure and ensuring data integrity in a pipeline scenario.>> Meanwhile for the (uncommented) code simplifies the logic by directly mapping input signals to output signals>> Answering your question, yes you can - depends on your application and needs. As long as the compilation PASS , it shall be no problem.Regards,WIncent_Altera

where to find testbench with Scalable Switch Intel® FPGA IP for PCI Express?

12 Replies

Wincent_Altera
Regular Contributor
7 months ago
Hi,
Which simulator that you try to use ?
You may find the simulation folder under ../xxx../switchIP/intel_pcie_sep_rtile_top_0_example_design/switch_ed/sim/
Please ensure that you enable the simulation tab upon design example generation

Let me know if you still unable to find it.
Regards,
Wincent_Altera
- wilson1977
  New Contributor
  7 months ago
  There is only a sim top file under switch_ed/sim directory,no testbench file.
  can you snapshot?
  - Wincent_Altera
    Regular Contributor
    7 months ago
    Hi Wilson,
    
    If you are refer to the xxx_tb.v file you can refer to switch_ed.v
    Let me know if I am not answering your question or I miss-understand anything.
    
    Regards,
    Wincent_Altera
Wincent_Altera
Regular Contributor
6 months ago
Hi,

Is there anything else you think I could help you ?

Regards,
Wincent_Altera
Wincent_Altera
Regular Contributor
6 months ago
Hi,

Let me know if you need more time to response to this cases.

Regards
Wincent_Altera
Wincent_Altera
Regular Contributor
6 months ago
Hi,

Given that there is no further reply from you after a few follow up, I sincerely hope you had solve the problem.
Please be understand that we are in full commitment to ensuring all of our client success.
IF you happen to get back to this issue and it is still not resolve, please submit a new thread, We will be there for you.

Regards,
Wincent

Forum Discussion

where to find testbench with Scalable Switch Intel® FPGA IP for PCI Express?

12 Replies

Recent Discussions

About Design Limitations and Known Issues

About Dual Simplex for Agilex 3

Where is High Speed Transceiver Demo Design in FPGA Wiki ?

Can't find Agilex 7 M I/O PLL Reconfiguration Design Example

Enabling DFE Adaptation on Cyclone 10 GX