New Contributor
Regular ContributorHi,
Which simulator that you try to use ?
You may find the simulation folder under ../xxx../switchIP/intel_pcie_sep_rtile_top_0_example_design/switch_ed/sim/
Please ensure that you enable the simulation tab upon design example generation
Let me know if you still unable to find it.
Regards,
Wincent_Altera
New ContributorThere is only a sim top file under switch_ed/sim directory,no testbench file.
can you snapshot?
Regular ContributorHi Wilson,
If you are refer to the xxx_tb.v file you can refer to switch_ed.v
Let me know if I am not answering your question or I miss-understand anything.
Regards,
Wincent_Altera
New ContributorThere are two demux_1stage_pipeline code under switch_user_logic/demux.v .The upper parts are commented.The lower parts are opened.
I want to use the upper parts code(commented). can it work?
// --------------------------------------------------------------------------------
// | single buffered pipeline stage
// --------------------------------------------------------------------------------
//module demux_1stage_pipeline
// #( parameter PAYLOAD_WIDTH = 8 )
// ( input clk,
// input reset_n,
// output reg in_ready,
// input in_valid,
// input [PAYLOAD_WIDTH-1:0] in_payload,
// input out_ready,
// output reg out_valid,
// output reg [PAYLOAD_WIDTH-1:0] out_payload
// );
//
// reg in_ready1;
// always @* begin
// in_ready = out_ready || ~out_valid;
// // in_ready = in_ready1;
// // if (!out_ready)
// // in_ready = 0;
// end
//
// always @ (posedge clk) begin
// if (!reset_n) begin
// in_ready1 <= 0;
// out_valid <= 0;
// out_payload <= 0;
// end else begin
// in_ready1 <= out_ready || !out_valid;
// if (in_valid) begin
// out_valid <= 1;
// end else if (out_ready) begin
// out_valid <= 0;
// end
// if(in_valid && in_ready) begin
// out_payload <= in_payload;
// end
// end // else: !if(!reset_n)
// end // always @ (negedge reset_n, posedge clk)
//endmodule //
module demux_1stage_pipeline
#( parameter PAYLOAD_WIDTH = 8 )
( input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_payload,
input out_ready,
output reg out_valid,
output reg [PAYLOAD_WIDTH-1:0] out_payload
);
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
out_valid <= 0;
out_payload <= 0;
in_ready <= 0;
end
else
begin
in_ready <= out_ready;
out_valid <= in_valid;
out_payload <= in_payload;
end
end
endmodule//
