Where to download XCVR IP Core for Cyclone 10 GX and updated design example?

Hi,

Thanks for your update and reference to the design in the Design Store. I am not sure what might be wrong when you use Q17.1.2 which lead to the issue that you are observing. However, to workaround this to allow you to proceed, I would like to suggest the following:

1. You can create a simple test design in RTL with ATX PLL + Reset controller + Native PHY

i. You may refer to the example design for the IP configuration

2. In the Native PHY, turn on the following in Dynamic Reconfiguration tab:

i. Enable dynamic reconfiguration

ii. Enable Altera Debug Master Endpoint

iii. On all the options under Optional Reconfiguration Logic

3. Connect the pinout following the example design

4. Create SDC for the top level design

5. After compilation and programming the design, you may try to use Toolkit to interface with the design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin