Where is the legacy interrupt enable/disable flag?

I'm trying to trigger an interrupt from a CycloneIV GX, using either an MSI if available, or a legacy interrupt. I've found the "MSI master enable" in cfg_msicsr(0) to know whether I should send MSIs, is there a similar flag somewhere to find out whether legacy interrupts are enabled (probably corresponding to the "Interrupt Disable" flag in the PCI configuration space's command register).

Looking at altpcierd_tl_cfg_sample, the most likely candidate would be cfg_prmcsr(10).

It is a bit unclear how cfg_prmcsr maps to the control and status registers, especially as table 5-14 on page 5-34 of the PCIe hard IP user guide shows that signal as 16 bit wide, when it is implemented as 32 bits.

Since cfg_prmcsr(26) is hardwired to 0, my expectation would be that the command register lives in the lower bits, similar to how the control register in the PCIe capability structure maps to the lower bits of cfg_devcsr.

Can anyone deny or confirm that this is the bit to look at when deciding whether interrupts should be flagged by asserting app_int_sts, or should I just invert the MSI enable bit and trust the hard IP to filter out interrupts while they are disabled?

Is the width of cfg_prmcsr an error in the documentation?