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Altera_Forum's avatar
Altera_Forum
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15 years ago

where is HDL SubSystem in DSP builder

Hi, I am new to DSP builder and FPGA programming. I was following DSP builder example which was on implementing FIR filter using DSP builder in Simulink and generating VHDL to be implement in m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

All I want to do is to design FIR filter in simulink.... and I dont seem to find any document that shows steps on desiging FIR filter on simulink like the one mention in this document....could you help me find such document....