when i tried to import the hdl file to simulink, i got the following error message

I was having the problem with the "Unable to resolve name XXX as a wire or I/O". I tried a few things but here's the one that seems to have worked. The signal it was complaining about was the clock half of an input data/clock serial stream. It ran into a dual-clock fifo that synchronized the data with the main system clock. The same clock also ran into a module that estimated the input data rate by counting edges of this clock using the main system clock. In short, it was used as both a clock and non-clock signal.