when i tried to import the hdl file to simulink, i got the following error message

sorry. The simulation without HDL import blocks works well.

I copied the missing files "libmex.dll libmx.dll dwmapi.dll" to the directory "..\dsp_builder\bin" and complied the module again. This time, the message box said " Error generating simulation model.

DSP Builder Fatal Error: uart: Unable to resolve name 'wrn' as a wire or I/O"

Is there anything wrong with the verilog source code? I download the code from website and it can be synthetized successfully in Quartus II.