What is the secret to how the VIP Scaler works, and can it handle 4:2:2 video?

rmatsick,

I totally agree with your conclusions on the VIP suite. We had previously done some DVI video processing where we implemented everything in Verilog ourselves, and were able to run through a Cyclone III FPGA at up to 165MHz with only 4-5 pixels worth of latency for an entire complex video processing chain. We recently ran out of funding on a project here due to the fact that we wasted several man months fighting with the VIP cores trying to process NTSC video, only to learn time after time that it did not support 4:2:2 or did not support interlaced video properly. Most of the VIP cores only seem to work well with progressive RGB video. In the long run I am spending my own time off the clock rewriting the project in straight Verilog.

The VIP suite looks great on paper, but there are so many little caveats that are not documented, and my experience is that the timing of the VIP processing chain is very very touchy and requires a lot of carefully implemented constraints to build an FPGA that works properly. And all this was for NTSC video. I would hate to try using it for 165MHz DVI!

I think that the people who are using the VIP successfully are probably using it with one of the larger and faster FPGA's like an Aria or Stratix, and they are using DDR2 or faster frame buffers to help the VIP chain run without underflows.

In my case I have a Cyclone -8 speed grade with SDRAM (16Mx16 at 133MHz). In theory it is plenty of horsepower for processing NTSC video - 27MHz 8 bit or 13.5MHz 16-bit, but sadly I am finding that it is not enough to handle much using the VIP cores.

Jim Morris