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JRubi5's avatar
JRubi5
Icon for New Contributor rankNew Contributor
6 years ago

What is the proper way to interface in Quartus Prime Platform Designer the avalon_st_rx and avalon_st_tx ports in a Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core.

These Avalon ports are built as Conduits in the Ethernet IP, and not as Avalon Streaming ports. The streaming clock signal is included in the Conduit.

My own IP needs to have an Avalon Sink port and an Avalon Source port. These two ports are clocked by the same clock. I have modified the Sink Port in my IP to be a conduit instead, which will be driven by the Ethernet conduit. But because the streaming clock is bundled in the Ethernet's conduit, I have no Avalon clock signal to use as a clock reference for the Avalon Source port.

3 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi, I believe you are referring to the clk_txmac & clk_rxmac, these are the output clock of the LL 100G Ethernet. Since this is a conduit port, you can actually connect it back to the platform designer via the clock bridge IP, so that you can use for other purpose. Regards -SK
  • JRubi5's avatar
    JRubi5
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks for your effective answer.

    I have defined in the VHDL design file the following port signals, compliant with the standard Avalon nomenclature:

    Csi_StClock_clk : in std_logic;

    Cso_StClock_clk : out std_logic;

    I have made this assignment in the architecture:

    Cso_StClock_clk <= clk_rxmac;

    where clk_rxmac is bundled among the signals in the Conduit that is driven by the Ethernet IP.

    Then in Platform Designer I have signal Cso_StClock_clk drive the input of a clock bridge IP. The output of the clock bridge IP drives Csi_StClock_clk, and this is the signal specified as a clock for the various Avalon source ports in the Signals and Interfaces tab of the Component Editor.