What is the proper way to interface in Quartus Prime Platform Designer the avalon_st_rx and avalon_st_tx ports in a Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core.

Thanks for your effective answer.

I have defined in the VHDL design file the following port signals, compliant with the standard Avalon nomenclature:

Csi_StClock_clk : in std_logic;

Cso_StClock_clk : out std_logic;

I have made this assignment in the architecture:

Cso_StClock_clk <= clk_rxmac;

where clk_rxmac is bundled among the signals in the Conduit that is driven by the Ethernet IP.

Then in Platform Designer I have signal Cso_StClock_clk drive the input of a clock bridge IP. The output of the clock bridge IP drives Csi_StClock_clk, and this is the signal specified as a clock for the various Avalon source ports in the Signals and Interfaces tab of the Component Editor.