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JRubi5's avatar
JRubi5
Icon for New Contributor rankNew Contributor
6 years ago

What is the proper way to interface in Quartus Prime Platform Designer the avalon_st_rx and avalon_st_tx ports in a Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core.

These Avalon ports are built as Conduits in the Ethernet IP, and not as Avalon Streaming ports. The streaming clock signal is included in the Conduit. My own IP needs to have an Avalon Sink port an...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, I believe you are referring to the clk_txmac & clk_rxmac, these are the output clock of the LL 100G Ethernet. Since this is a conduit port, you can actually connect it back to the platform designer via the clock bridge IP, so that you can use for other purpose. Regards -SK