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Altera_Forum's avatar
Altera_Forum
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16 years ago

what is the circuit of 2^n -1

these is a problem for me,i need some help.

how can i use verilog describe 2^n -1

the input interface is input[3:0] n;

the output interface is output [15:0] result;

i know can use a table ,but these is some other describe

thanks

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    this is also a ROM

    can it describe wtih register?

    --- Quote End ---

    What I wrote wouldn't be synthesized as a ROM (in an Altera FPGA) since it's not synchronous. Instead you'll get the same muxing logic only the result isn't registered. Here is a good doc to take a look at to learn more about HDL coding styles and how they map to the FPGA logic: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

    The short forms using the shift operation I suspect will synthesize into the same multiplexer structure from the case statement. A variable shift operation (barrelshift) is a multiplexer of the same data under different shift distances. The shift amount maps to the select bits of the mux.

    Like others have said try various codings and see if any give better results. It's easier to try various things and let synthesis do all the heavy lifting instead of the other way around :)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I don't assume significant differences in the synthesis results. The expression for each output signal should fit a 4-input -LUT, so it can be expected, that all logical equivalent descriptions end up in the same circuit.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    What I wrote wouldn't be synthesized as a ROM (in an Altera FPGA) since it's not synchronous. Instead you'll get the same muxing logic only the result isn't registered. Here is a good doc to take a look at to learn more about HDL coding styles and how they map to the FPGA logic: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

    The short forms using the shift operation I suspect will synthesize into the same multiplexer structure from the case statement. A variable shift operation (barrelshift) is a multiplexer of the same data under different shift distances. The shift amount maps to the select bits of the mux.

    Like others have said try various codings and see if any give better results. It's easier to try various things and let synthesis do all the heavy lifting instead of the other way around :)

    --- Quote End ---

    BadOmenthank you very much .

    As you said,it will synthesize into the same multiplexer structure from the case statement

    so if i interface a ROM

    it can save so much resource ?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    That is correct, you can use a small ROM as a lookup table based decoder. Just follow the ROM coding style in that link I posted. Keep in mind that this ROM will have a latency of one clock cycle.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    A ROM is an option of course, but what do you mean with "save so much resource"?