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What I wrote wouldn't be synthesized as a ROM (in an Altera FPGA) since it's not synchronous. Instead you'll get the same muxing logic only the result isn't registered. Here is a good doc to take a look at to learn more about HDL coding styles and how they map to the FPGA logic:
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf The short forms using the shift operation I suspect will synthesize into the same multiplexer structure from the case statement. A variable shift operation (barrelshift) is a multiplexer of the same data under different shift distances. The shift amount maps to the select bits of the mux.
Like others have said try various codings and see if any give better results. It's easier to try various things and let synthesis do all the heavy lifting instead of the other way around :)
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BadOmenthank you very much .
As you said,it will synthesize into the same multiplexer structure from the case statement
so if i interface a ROM
it can save so much resource ?
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