what do you mean by "single I/O column" in Stratix 10 GX fpga?

Hi @hb0001​ ,

If I understand correctly, you are referring to below PFL IP. The bank is varies depend on the device's OPN. You need to connect it using dedicated config pins (example shown in Figure below) . For more details , you may checkout this Stratix 10 UG (start from page 40) --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-config.pdf#page=40&zoom=100,0,0

In Table 2 of the pin connection guideline handbook, there is a list of this dedicated config pins. You can check this config pins located at which bank number in the Intel FPGA Pin-out file. Kindly refer to link provided below.

Pin Connection Guideline --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf

Pin-out file for Intel FPGAs--> https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

Regards,

Aida