what do you mean by "single I/O column" in Stratix 10 GX fpga?

Hi @hb0001​ ,

I think @sstrell​ have a point. 😊

This is just for your additional reference, you may refer to section "3.1.2. Intel Stratix 10 EMIF Architecture: I/O Column" in this UG , refer to Figure 3 for architecture of Stratix 10 I/O Column.

UG link--> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pdf

Hope this helps.

Thanks

Regards,

Aida