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hb0001
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6 years ago

what do you mean by "single I/O column" in Stratix 10 GX fpga?

I didn't get the line in EMIF IP manual "Ensure that the pins of a single external memory interface reside within a single I/O column." Please explain..
hb0001's avatar
hb0001
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6 years ago

As S10 is devided into 3 i/o lanes, I wanted to know how these i/o lanes are divided in s10.

hb0001's avatar
hb0001
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6 years ago

sorry 3 i/o columns.