what do you mean by "single I/O column" in Stratix 10 GX fpga?

I/O in S10 are arranged in columns which are organized into banks, which are in turn organized into 12-pin I/O lanes. You use one or more banks to implement an EMIF, but you want those banks to all be in the same I/O column in order to meet timing and make sure the interface works. You can have multiple memory interfaces in the same column (which in some cases allows you to share resources to implement the multiple interfaces), but you can't have a single interface span multiple columns.

See this online training for an overview of the EMIF architecture and implementation:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1121.html

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