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Altera_Forum
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17 years ago

What are oct_ctl_rs_value's and oct_ctl_rt_value's?

Hello,

I am struggling to get a StratixIII DevKit design running with the DDR2 High Performance Controller. I reproduced all settings from the stratixIII_3sl150_dev_niosII_standard factory example design. Even though, the design compiles fine, a simple NiosII test application fails on software download. 


Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: OK
Reading System ID at address 0x10001040: verified
Initializing CPU cache (if present)
OK
Downloading 04000040 ( 0%)
Downloading 04010000 (67%)
Downloading 0C000000 (91%)
Downloaded 95KB in 1.6s (59.3KB/s)
Verifying 04000040 ( 0%)
Verify failed between address 0x4000040 and 0x400FFFF
Leaving target processor paused

I guess, there might be a connection with on-chip-termination. I wonder, why the SOPC builder generates the following ports in the SOPC top level entity.

For instance: 


oct_ctl_rs_value_to_the_ddr2_data
oct_ctl_rt_value_to_the_ddr2_data

In the factory example these signals are not present. So, I don't know what to do with them. I just set them to (others=>'0').

Could this be the reason, why the Nios CPU is not responding, nor working?

Could anybody please help! I'have already spent days on this issue, and I don't make any progress.

P.S. I know that the factory example works, indeed. So, the only difference between my design and their design is this oct_ctl signal stuff.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I just found out that the SOPC builder generates this oct_ctl signal in the SOPC design entity. However, in the top level entity of the factory example, they are not mentioned in the Verilog code. I guess, they are just ignored.

    In VHDL there must be an assignment to input ports. So, I set them all to 0.

    Also, I found out that my design and the factory example seem to produce the same synthesizer and fitter warning concerning this issue. Some signals with "ctl" as part of their name (and therefore I think they might be a connection to this oct_ctl signals) produce stuck at warnings.