What are oct_ctl_rs_value's and oct_ctl_rt_value's?

I just found out that the SOPC builder generates this oct_ctl signal in the SOPC design entity. However, in the top level entity of the factory example, they are not mentioned in the Verilog code. I guess, they are just ignored.

In VHDL there must be an assignment to input ports. So, I set them all to 0.

Also, I found out that my design and the factory example seem to produce the same synthesizer and fitter warning concerning this issue. Some signals with "ctl" as part of their name (and therefore I think they might be a connection to this oct_ctl signals) produce stuck at warnings.