VIP Scaler problems....

Could you describe your system in a little more detail?

1 - What version of the tools and IP are you using?

2 - What FPGA are you using and what speed grade?

3 - You are displaying a static 720x288 image. How many bit per pixel? I assume this is RGB.

4 - You are reading data from RAM. What kind of RAM? How wide is the interface? What speed is it running at?

5 - The FIFO. Is this a single-clock or dual-clock FIFO? How fast are you running it? How deep is it?

6 - The scaler, what algorithm are you using? What is your scaling factor?

7 - You're output block. What are you using as an output block (VIP clocked video output or home-brewed)? How fast are you running it? What is the output standard of the VGA (resolution)? What are your settings for sync, front porch, back porch, etc.?

8 - Do you have any FIFO between the scaler and your output block?

9 - Do you have anything in the Video processing path that inserts VIP control packets (information needed by the scaler to provide input/output resolution).

10 - If you are not using the VIP clocked video output? Do you have anything in the path to remove the video control packets?

Altera has provided video component blocks but video processing is very much a system design problem rather than a component design problem.

Jake