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Altera_Forum
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15 years ago

VIP FrameBuffer - How do you think it is accessing the SDRAM?

Hi!

I am thinking about FrameBuffer Core Altera provides. In the VIP User Guide it is explained clearly, how the FB is working, with the concepts of dual and triple buffering.

What I don't understand is, how Altera could get the FB working with only one SDRAM. So my problem is, I want to implement a system, where I write Video-Data into SDRAM and read it with the FrameReader to output it with a CVO. My system should be:

... -> Writer -> AccessArbiter(SDRAM) -> FrameReader -> CVO

I don't get it to work this way, because the Altera SDRAM-Controller Core is running only with 100Mhz max. My system runs at 100Mhz, too. So I need two SDRAM to manage read and write and switch them by a selfwritten AccessArbiter every Frame, like a dual buffer. My actual system looks like this:

... -> Writer -> AccessArbiter(SDRAM0, SDRAM1) -> FrameReader -> CVO

How do they get it to work with only one SDRAM? Anyone has an idea?! I have thought about this some time now and don't find a solution. Everything I tried with FIFOs got me overflows, because the SDRAM adds to much cycles while writing and reading.

Any advise would be appreciated.

Thanks, Peter.

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Kevin, I am not thinking that there is a major bug in the code. I have developed that with modelsim and got it worked out according to the avalon specifications.

    You are mentioning to use burst transfers. I am not doing this, because in the documentation of the SDRAM Controller Core it is just mentioned, that it supports pipelined access. I looked in the documentation that I have got again and did not find any hint for bursts, why do you think it supports it? Have you got any source?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Whether the memory controller supports bursts to the memory or not, performing bursts on the Avalon bus will increase the efficiency.

    With SDRAM, there are extra delays whenever you change addresses or change from read to write. If you perform small random reads or writes, the effective data rate will be much less than your memory clock speed.

    For example, writing and reading 10 words each alternating between read and write will be much slower than writing 10 words consecutively followed by reading 10 words consecutively.

    Using bursts on your avalon master port will ensure more consecutive access to memory. Another way that might work is to change the arbitration shares in SOPC builder and use pipelined access.