Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VIP Frame buffer & HPC II ddr2 problem

I've been building up a VIP video system in SOPC builder with QII ver10.1. I am having a problem getting the external ddr2 to run. I have checked all the normal hardware types of things... (power, clocks, resets, etc...) and it seems fine. The fpga is working as I have been able to talk to the various modules via their AvMM control ports. I have also been able to use the Test pattern generator and the ITC to generate color bars on my monitor...

The problem is when I put the frame buffer in with the pipeline bridge and HPCII ddr2 memory controller. It looks as if the external parts go through initialization but after that the only signals that I see are the clocks. I've looked at the top level signals available to me on the SOPC top level module and see the two resets (global_reset_n_to_the_altmemddr_0 and reset_n)... I was thinking that I should drive the global_reset_n_to_the_altmemddr_0 first then use the corresponding reset_phy_clk_n_from_the_altmemddr_1 signal with some of my logic to generate the reset_n signal ... I've used the HPC controller in my own IP before and always use the reset_request_n to generate the other resets on in the system. This would ensure that I didn't generate any read_reqs or write_reqs before the memory PLL was locked.... but the documentation says that the two reset inputs should be tied together so I'm not sure if this has any bearing on my problem...

Anyway, I'm not getting the system setup correctly it seems and could use some help. I've been using the UDX2.1 Video IP Training Lab material as a guide to set this up, but I missing something.... Any guidance would be greatly appreciated

thank you,

david coburn

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    A little more information .....

    I have gone back to a HPC with altmemphy setup that I have used many times from the megawizard... It seems that the local_init_done signal never goes high which tells me that the ddram is not getting calibrated, or initialized or something correctly at the beginning...

    The issue above then causes the VIP Frame buffer to fill it's fifo as the CTI puts in data and when the FB fifo gets full it drives the ready signal low and holds off the CTI... but the real issue is the ddr not getting brought up correctly....

    Any thoughts on this?

    thanks,

    david
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Outside of SOPC builder you should get a generated example top project with Altmemphy and an altera test driver. I would check this is working first. If it is then its likely that you have a problem connecting clocks or resets within SOPC builder.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    std logic,

    thank you for the reply. I should have posted that I got it working... basically it was my fault in simply not being careful enough. I had configured the HPC II memory incorrectly...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I have a doubt.

    Is the frame buffer itself to control the data flow if i have a pattern generator as an input data and a clocked video output as an output data? (both from the VIP).

    or Is it necessary to use the Nios II for this case?

    I tested the HPC II ddr2 controller out of QSys and is working, but when I integrate all these cores in Qsys I dont see anything.

    Thank you,

    Juan