Honored Contributor
Honored ContributorThankyou - I have now seen this information in the datasheet. It seems to give rough characterizations for Cyclone and Stratix devices. I am guessing that the Arria2 devices must be somewhere in between?
Assuming this, it would seem that 187 MHz may be on the hairy edge for this family. In a fairly full design, I suppose meeting timing may be a challenge anyway. Pipelining would be the normal approach, but from my understanding, 11.1 SOPC Builder does not really support the option of insertion of pipelining stages for all IP blocks. My understanding is that QSys offers more options on this front. Am I right?
