Altera_ForumHonored Contributor9 years agovip cores, downscaler and upscaler Dear, I'm doing vip cores to realize the downscaler. Quartus14.0, cycloneV, clocks: nios_cpu_clock- 100MHz, avslon_st_clk- 150MHz, avalon_mm_clock- 100MHz. 1.down...Show More
Altera_ForumHonored Contributor9 years agoThe upscaler's vip seeting are in the attachments.multiple-attachments.zip61 KB
Recent DiscussionsError when simulating F-tile Ethernet example designAvalon Transaction Responses & BridgesSerialLite II license for Arria10 FPGAAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedCORDIC ATan2 Failed to Generate