Honored Contributor
Honored ContributorHi Gareth,
I've finally burned down my list of things to implement, and i'm back where i started. I've tested the hs, vs, data_en and clk out of the video decoder and they are SOLID as a rock. there is no jitter or movement in the hs signal, neither within or outside a vs active period. The issues I am seeing appear to be caused elsewhere. I'm chasing as many timing possibilities as I can; I'm only new to Timing Quest so it's slow progress. One interesting thing is that i've managed to introduce a bug where the vertical lines appear overlaid on the screen; while there is significant colour distortion (in Quartus 9.0sp2.) So I concede that there is definitely a problem with my video input, probably the same one I was seeing in Quartus 9.1sp1. Also, I am now consistently reading these conditions from the CVI control port: Status register = 0x9 - Running - Sample count valid - Line count NOT valid - Progressive - NOT stable Used words: 0 or 1 only Sample count = 0x320 (correct for this test) Line count = 0 Does this give a fingerprint of a common issue? I'm going to pursue the internals though signal tap and will post more info later.
