I am having some problems with the VIP CVO IP. My QSYS core frequency is 100Mhz But my CVO IP output must run at a different frequency. Initially I used 44.8Mhz And it seemed to work ok. However, when I doubled the CVO clock in to 89.6 It stopped working – the LPDDR2 would not calibrate, etc. etc. Again, I’m applying An external clock to the CVO (ITC) expecting it to sync between the internal 100Mhz And external 89.6Mhz. I did not configure for a control port and simply relying on The width/height, etc. setting which are not standard. Does it mean that the system Can’t keep up with to 89.6? should I increase it to 120Mhz. Thanks, S.

What does the FIFO-Underflow signal say? If you have an underflow, maybe an increasing of the clock would help, but please share some insights of your whole systemdesign to give us a better view of maybe improvements regarding your design. And maybe you want to have a look to the timing-analysis of your design...

Thanks Taz1984, I got it all working ! Instead of using the external clock I simply ran the ITC/CVO on the same streaming clock which I increased to match to the external clock freq. I still have in the design the "Sequencer IP" which requires a license... it does not do very much other than discard the upper byte of the 32bit coming in from the Frame-Reader and going to the CVO. Can I do away with not using it? This is preventing me from putting the design into FLASH. My next task is loading an image into LPDDR but FAST. I am now using an external bridge (the Master on the Avalon-MM bus) to an SPI interface. It takes 20min to load into LPDDR... Any suggestions?

You may write your own sequencer to get rid of the one with license-fee, should not be that hard to write. To give you a hint regarding the loading an image to the ddr, I need to understand your whole system-design first. -Which Chip do you use? An SoC with HPS, do you have a NIOS in your design? -Which width and height does the image has? -Do you just want to show an image, or several changing images, or a live-stream of a video source?

Thanks Taz. How do I write my own sequencer or any other Avalon ST module and integrate it into the lib? Are there any examples for doing that? The main issue with loading the DDR in my case is that I don't have a NIOS II in the system. I use an external master/bridge, etc. this slows down the process because of the use of Python script. So I think that I'm going to add a NIOS II to the system and download the large image file using it. (1920*720*2=2764800pixels, *4bytes=11MegB per image) It would have been nice to download the image through using In-System Memory Editor but that is only for SRAM. The JTAG/SPI access way is too convoluted to use. Thanks, Jacob

--- Quote Start --- Thanks Taz1984, I got it all working ! Instead of using the external clock I simply ran the ITC/CVO on the same streaming clock which I increased to match to the external clock freq. I still have in the design the "Sequencer IP" which requires a license... it does not do very much other than discard the upper byte of the 32bit coming in from the Frame-Reader and going to the CVO. Can I do away with not using it? This is preventing me from putting the design into FLASH. My next task is loading an image into LPDDR but FAST. I am now using an external bridge (the Master on the Avalon-MM bus) to an SPI interface. It takes 20min to load into LPDDR... Any suggestions? --- Quote End --- Hi Shvitzer, Firstly it is not clear what you are doing. Secondly it is not clear which clock domains in the system you have. Not talking about the Sequencer IP..what is that? Are you talking about the Color Plane Sequencer? Next, how do you use LPDDR? Do you put your frame there to be used by the Frame Reader? You connect your FR to LPDDR and use Nios II. It is cheap (E is free) and nasty .....

VIP Clocked Video Out Problem | Altera Community

12 Replies

Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
The FR reads 32bit from DDR of which only 3*8=24 are needed that is where the CPS comes in to discard the upper 8 bits and stream only 24bits to the CVO. Yes, I can configure the FR to send only 3 color planes directly to the CVO, all compile, but no video comes out!!!
--- Quote End ---

Did you make any others changes in project when you change FR configuration from 4 bytes to 3 bytes?
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
Thank you guys for trying to help, however, I am getting more questions than answers here and little or no help. Let me clarify something: my VIP design works now, however, I can not afford the license fee for the CPS so I am looking for ways to get rid of it or design my own. The FR reads 32bit from DDR of which only 3*8=24 are needed that is where the CPS comes in to discard the upper 8 bits and stream only 24bits to the CVO. Yes, I can configure the FR to send only 3 color planes directly to the CVO, all compile, but no video comes out!!!

Regarding the SD card controller (nothing to do with the above) Quartus/QSYS is missing the files I mentioned. Just Google the problem and you will see that others ran into the same problem. Please don't ask me if I know what I am doing, that is rude. Try to answer the question only if you can.
--- Quote End ---

Shvitzer,
I am answering here because I have experience working with the Frame Reader and I never used CPS. Just trying to help. You have to find the root of the problem in using FR. It is parameterized using Nios II. Small Nios is free and doesn't use too much logic.
Regarding SD card I didn't mean to be rude. I just asked if you know what you doing. If yes then It is a quartus BUG and you should look for a fix. Check the Quartus version and look at the knowledge database. Probs you can find these files and put them manually to the Qsys synthesis directory as a temporarily fix.

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VIP Clocked Video Out Problem

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