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Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Thanks Taz1984, I got it all working ! Instead of using the external clock I simply ran the ITC/CVO on the same streaming clock which I increased to match to the external clock freq. I still have in the design the "Sequencer IP" which requires a license... it does not do very much other than discard the upper byte of the 32bit coming in from the Frame-Reader and going to the CVO. Can I do away with not using it? This is preventing me from putting the design into FLASH. My next task is loading an image into LPDDR but FAST. I am now using an external bridge (the Master on the Avalon-MM bus) to an SPI interface. It takes 20min to load into LPDDR... Any suggestions? --- Quote End --- Hi Shvitzer, Firstly it is not clear what you are doing. Secondly it is not clear which clock domains in the system you have. Not talking about the Sequencer IP..what is that? Are you talking about the Color Plane Sequencer? Next, how do you use LPDDR? Do you put your frame there to be used by the Frame Reader? You connect your FR to LPDDR and use Nios II. It is cheap (E is free) and nasty .....