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Altera_Forum
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10 years ago

VIP Clocked Video Out Problem

I am having some problems with the VIP CVO IP. My QSYS core frequency is 100Mhz But my CVO IP output must run at a different frequency. Initially I used 44.8Mhz And it seemed to work ok. H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks Taz. How do I write my own sequencer or any other Avalon ST module and integrate it into the lib? Are there any examples for doing that?

The main issue with loading the DDR in my case is that I don't have a NIOS II in the system. I use an external master/bridge, etc. this slows down

the process because of the use of Python script.

So I think that I'm going to add a NIOS II to the system and download the large image file using it. (1920*720*2=2764800pixels, *4bytes=11MegB per image)

It would have been nice to download the image through using In-System Memory Editor but that is only for SRAM. The JTAG/SPI access way is too convoluted to use.

Thanks,

Jacob