VIP Clocked Video Input Malfunction?

You can run signaltap with a time-limited design. You either have to disconnect from the design (in which case it will usually run for an hour) and then run signaltap or you can start another instance of Quartus and run signaltap from there.

One thing you might consider doing is to put a small dual-clock FIFO outside your SoPC system. Bring the raw video data into the FIFO using the video clock. Then clock the output of the FIFO using your system clock and going into your CVI block. Use the negation of the rdempty signal from the fifo as the datavalid signal into the CVI block. Use the locked signal to clear the FIFO. This will do two things:

1 - Provide a constant,reliable clock to the CVI block.

2 - Allow you to run the CVI block in single clock mode.

Jake