Forum Discussion
Honored ContributorVideo IP Scaler control
Hello,
I'm having trouble using the Scaler in the Video IP suite. I have instantiated the scaler using the megawizard and my control logic is custom. I have instantiated a fixed scaler in my system and it works just fine (no input or output sizes needed on the ST or MM interfaces). When trying to set the input and output image sizes the scaler accepts the first few pixels and then deasserts din_ready never to assert it again. I am configuring the scaler in the following way. Reset Scaler. Avalon MM interface : Set go bit to zero. Wait for status bit to be zero. Set the go bit to one. Avalon ST interface : Send control packet (startofpacket & Data = 0xF) Send Width and Height nibbles. Send control packet (endofpacket & Data = 0x0(progressive)) Send control packet(startofpacket & Data = 0x0(Video data)) start sendig data. the scaler takes 3 pixels and then deasserts din_ready and the video flow stops. How do the width and height nibbles fit into a parallell data stream of 8 bits per pixel and 3 color planes in parallel. the documentation is a little unclear and I have tried some different nibble groupings. Any help or pointers would be greatly appreciated ! Thanks :D21 Replies
Altera_ForumThanks again Jake,
Here are some waveforms (attached pdf) of the Avalon ST and MM interfaces as they are being programmed in my system. Should be easier to see this way :D- Altera_Forum
What I think would be more telling is a signaltap shot of the av-st interfaces both into and out of the chip for the duration of the control packet, and the beginning of the video packet.
Jake - Altera_Forum
Jake,
Here is the snap of the AV-ST interface where we see the control packet going in and out of the scaler. The scaler drops din_ready after a couple of din_valid's and does not reassert ready. thanks again for your help....... ks - Altera_Forum
Okay there is your problem. With avalon streaming interfaces, there is the notion of "ready latency". The VIP components use a ready latency of "1" on the AV-ST interfaces. Your screenshot shows your are using a ready latency of 0.
Please reference section 6.3 of: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf and page 4-11 of the VIP user guide: http://www.altera.com/literature/ug/ug_vip.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=ug_vip Jake - Altera_Forum
I think I am following the ready latency of 1 as specified. In each case I am supplying din_valid one clock cycle after din_ready, that is the way the logic is setup anyhow.
What specifically am I doing wrong ? Hopefully it is wrong I would like to get this working..... thanks again for the replies. ks - Altera_Forum
My apologies. I got confused looking at the waveform and mistaked din_valid for din_ready. You are correct, you are adhering to the ready latency of 1.
Have you tried reading the status register of the scaler to see what it claims? Jake - Altera_Forum
Good Idea I'll give that a try. I read somewhere that the output width and height (Regs 2,3) of the scaler are write only do you know if you can read them ?
thanks again.... ks - Altera_Forum
I would treat them as write only. If I remember correctly from discussions with the video IP designers that it actually depended on which device family you were using. And if memory serves it seems if you try to read them all you get back is 0xffffffff. But it will be interesting to see if the status register claims that it is outputting video data.
Jake - Altera_Forum
Status register is indicating that it is not busy, Status[0]=0 :rolleyes: although I am giving it the startofpacket with 0x0 (video) type.
thanks, ks - Altera_Forum
Have you also read the go bit back from the control register to verify it got set?
