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SSchm28's avatar
SSchm28
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5 years ago

Video and Image Processing Suite - can't fit design / can't read "fifo_type": no such variable

Hello, I have two projects with an Cyclone 10lp16k FPGA using the VIP ip cores from intel. I develop with the Quartus Prime Lite 20.1 version (Windows). In the first project, compilation and fit...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


May I know do you able to isolate which VIP IP solution and which parameter setting in the IP is causing fitter error here ?


Also can you shared with me both your fitter passed and fitter failed Quartus design QAR file so that I can duplicate failure in house and debug them ?


Thanks.


Regards,

dlim


SSchm28's avatar
SSchm28
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5 years ago

Hello,

I assume that the clocked video output ip core cause the problem.

I prepared 2 projects, one works fine. the other will fail during fitting.

If you remove the "alt_vip_common_fifo.sdc" file in "db\ip\TPG\submodules\modules\alt_vip_common_fifo\src_hdl" before fitting the failing one should also work.

Both projects are basically the same. There is one Platform Designer subsystem "TPG" with just a Testpattern Generator and an Clocked Video Output and a second subsystem for video processig with a CVI - Clipper - Framebuffer -SDRAM Controller and CVO.

If you include the Video pipline the project will compile fine , if you comment it out it will fail during fitting.

With best regards

Sebastian Schmitz