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Altera_Forum
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14 years ago

VHDL output given when Verilog requested

Hi I'm currently going through the motions of getting a DDR3 controller for the Arria II GX development board. I'm using Quartus 11.0 and I've used the MegaWizard thing to generate the RTL...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The primary interfaced module should be Verilog, if requested, but it's only a wrapper. The IP core consists of a number of files, that may be either Verilog or VHDL, depending on the respective Altera Megafunctions.

For a functional simulation, you need to use special simulation files that are replacing the encrypted part of the IP core.