VHDL Code Generation and Design Partitions

Hello,

I try to work with design partitions in Quartus. The VHDL code is generated with DSP Builder 10.1 SP1. The problem is that DSP Builder always generates different VHDL code, even when nothing changes in DSP builder design. After that Quartus wants to recompile that code which makes usage of design partitions pointless.

So how to work with design partitions and DSP Builder ?

P.S.

I have one big design in DSP Builder and don't want to break it up in many design files.

Best Regards