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Altera_Forum's avatar
Altera_Forum
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16 years ago

Verilog module Instantiation

Don't really know whether i should post this Q here or not. I'm a student using modelsimSE 6.1f. actually this Q is more to verilog...not on fpga hardware issue i was wondering,how can i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I am getting error while instantiating modules on condition with the default module. it is giving error if i instantiate default mode.

the code is much similar to this:

module top(//parameters);

addition u0(//parameters passing); line 2

'ifdef(flag)

sum u1(//passing the parameters);

'else

subtract u2(//passing the parameters);

'endif

endmodule

if the module addition-u0 is removed, then only code is working properly. but i need to operate before conditional execution.

plz help me.:cry: