Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Verilog module Instantiation

Don't really know whether i should post this Q here or not. I'm a student using modelsimSE 6.1f. actually this Q is more to verilog...not on fpga hardware issue i was wondering,how can i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

btw,it's all working now...tq^^

added A1 and B1 to the output port to simulate it and it runs well

without the clock generation