Verilog module Instantiation

module bin2bcdAdder(input1,input2,bcd);
   input  input1,input2;
   output  bcd;
  wire  S;
  wire  input1,input2; /*without this line, i can't assign the input values to A1,B1 and compile the code*/
   reg  A1,B1;
addminus4bit am4b(A1,B1,0,S,V,C);
always @ (A,B) // without a clock input this will NEVER work
begin 
if((A>4'b1001)|(B>4'b1001))
begin
   A1<=4'b0;  // proper assigments
   B1<=4'b0;  //proper assigments 
end
else
begin 
   A1<=input1;  // proper assigments
   B1<=input2;  // proper assigments
end
/*some codes here*/
end
endmodule