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Altera_Forum
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15 years ago

Verilog module Instantiation

Don't really know whether i should post this Q here or not. I'm a student using modelsimSE 6.1f. actually this Q is more to verilog...not on fpga hardware issue i was wondering,how can i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

module bin2bcdAdder(input1,input2,bcd);
input  input1,input2;
output  bcd;
wire  S;
wire  input1,input2; /*without this line, i can't assign the input values to A1,B1 and compile the code*/
reg  A1,B1;
addminus4bit am4b(A1,B1,0,S,V,C);
always @ (A,B)
begin 
if(A>1001|B>1001)
begin
A1=4'b0;
B1=4'b0;
end
else
begin 
A1=input1;
B1=input2;
end
/*some codes here*/
end
endmodule
well,i tried using the always block...

or is it useless to use the > comparison?

do i need to do case for each bit from 0000 to 1001?