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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog module Instantiation

Don't really know whether i should post this Q here or not. I'm a student using modelsimSE 6.1f. actually this Q is more to verilog...not on fpga hardware issue i was wondering,how can i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You basicaly need to add soething like this somewhere in your code

if (input == 1001) begin

input <= 4'b0;

end

But I guess you have no clue where to add it right ?

Well, I can not help you there, not without the code.