verilog- parameterized mux

Hi Rysc,

jakobjones suggested:

module mux (#parameter  WIDTH           = 8,
           # parameter  CHANNELS        = 4) (
    input         in_bus,
    input       sel,   
    output                   out
    );

but I am implementing slightly differently. To continue jakobjones' example it would be:

module mux 
(
in_bus,
sel,
out
);
parameter WIDTH = 8;
parameter CHANNELS = 4;
input  in_bus;
input  sel;
output  out;
//define the clogb2 function
function integer clogb2;
  input depth;
  integer i,result;
  begin
    for (i = 0; 2 ** i < depth; i = i + 1)
      result = i + 1;
    clogb2 = result;
  end
endfunction

I haven't actually tried to synthesize jakobjones' example, so I cannot comment on its ability to be synthesized. However, my structure above which separates the port list declaration and their width definitions does synthesize. I will report however that I've been in the Xilinx world lately so I cannot comment on how the Quartus tools respond to the above example.

good luck, and let us know how it goes.

..dane