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Altera_Forum
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16 years ago

verilog- parameterized mux

For the life of me I cannot figure out how to generate a parameterized mux in verilog... I understand how to generate, say, a 4:1 MUX of "N" bits wide... But I am trying to generate an N:1 mux...
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Altera_Forum
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16 years ago

1 - That first "+" sign in the array declaration is a typo. See I told you there might be errors.

:).

2 - The second "+:" sign in the "assign" statement is legitimate and is called a "Variable Vector Part Select" operator.

For example, a statement like:

assign data1 = data[8+:8]

is equivalent to:

assign data1 = data[15:8];

Generically:

assign data1 = data[x+:y]

So the "+:" operator uses "x" as the starting index of the vector and uses "y" to determine how many bits of the vector to index. The "+:" operator adds "y" bits to "x" while the "-:" operand subtracts "y" bits from "x".

Jake

I will post some equivalent examples shortly.