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Altera_Forum
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16 years ago

verilog- parameterized mux

For the life of me I cannot figure out how to generate a parameterized mux in verilog... I understand how to generate, say, a 4:1 MUX of "N" bits wide... But I am trying to generate an N:1 mux...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I hope I'm not doing your homework for you. One of the shortcomings of Verilog is the inability to generate ports. So you have to bring the input in as a bus.

I haven't compiled this so there may be errors: 

module mux (#parameter  WIDTH           = 8,
           # parameter  CHANNELS        = 4) (
    input         in_bus,
    input       sel,   
    output                   out
    );
genvar ig;
    
wire     input_array ;
assign  out = input_array;
generate
    for(ig=0; ig<CHANNELS; ig=ig+1) begin: array_assignments
        assign  input_array = in_bus;
    end
endgenerate
//define the clogb2 function
function integer clogb2;
  input depth;
  integer i,result;
  begin
    for (i = 0; 2 ** i < depth; i = i + 1)
      result = i + 1;
    clogb2 = result;
  end
endfunction
endmodule