verilog- parameterized mux

I hope I'm not doing your homework for you. One of the shortcomings of Verilog is the inability to generate ports. So you have to bring the input in as a bus.

module mux (#parameter  WIDTH           = 8,
           # parameter  CHANNELS        = 4) (
    input         in_bus,
    input       sel,   
    output                   out
    );
genvar ig;
    
wire     input_array ;
assign  out = input_array;
generate
    for(ig=0; ig<CHANNELS; ig=ig+1) begin: array_assignments
        assign  input_array = in_bus;
    end
endgenerate
//define the clogb2 function
function integer clogb2;
  input depth;
  integer i,result;
  begin
    for (i = 0; 2 ** i < depth; i = i + 1)
      result = i + 1;
    clogb2 = result;
  end
endfunction
endmodule