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Altera_Forum
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15 years ago

Verilog - Digital Design Help!!!

I am working on a de-serial Design IP module, and I have to collect information into a single register containing Header + Message + CRC. I am receiving serial data which will bean header of 8 bits a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Does it need to be stored as a wide register? Normally you just deserialize the packet into memory and parse the data out from there.