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Altera_Forum
Honored Contributor
Honored ContributorVCD sink block doesnt generate VCD file
Hello All,
The VCD sink block says it generates a .vcd file and .tcl file for viewing the simulation result in third-party simulator. I have tried generating VCD file by connecting VCD sink block from Altera DSP builder to the desired ports in my design. After running a simulation all it generates is a .txt file. When I opened the file it contans simulation result in vector format. But it doesn't have any information about port name and all. Please I need to generate .VCD file for Powerplay analysis tool in quartus. Regards, Dilip2 Replies
Altera_ForumAre you using Linux? If so, then see the errata (http://www.altera.com/literature/rn/rn_dsp_builder_101.pdf). I think when it says HDL files, it means VCD files.
- Altera_Forum
Yes I found that VCD sink has a bug in linux version. Anyway now I am exporting the design to VHDL and calling Modelsim from Quartus tool to generate VCD. Thanks for your time.
