Honored ContributorHello
I'm using a CycloneII EP2C20 and want to dynamically control the output data rate from the fpga. I can't find a optimum solution to this, as the CycloneII doesn't have dynamic PLLs. Currently I have a fixed clock and a counter that waits X clock cycles before outputing a new data. It works but isn't very flexible because I'm limited to rate values of (Clock Rate/X) only. Any ideas? Thank you! Thiago
Honored ContributorBuild an NCO. Take an adder feeding back to itself (Accumulator) with a variable 'delta phase' on the other input. When the adder overflows, send your data. This gives you a fractional division of the PLL frequency. OutputRate=PLL_Freq*DeltaPhase/2^AdderBits. The more adder bits, the finer the resolution, but the adder has to work at speed also.
Honored ContributorHi,
depending on your application, i would use a serial configurable external pll. They typical have better perfromance than the internal PLLs. http://www.idt.com/?genid=307 ChristianHonored ContributorNice, thank you very much! =]
Thiago
