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Altera_Forum
Honored Contributor
Honored ContributorVariable Data Rate
Hello I'm using a CycloneII EP2C20 and want to dynamically control the output data rate from the fpga. I can't find a optimum solution to this, as the CycloneII doesn't have dynamic PLLs. Cur...
Altera_ForumHonored Contributor
Honored ContributorBuild an NCO. Take an adder feeding back to itself (Accumulator) with a variable 'delta phase' on the other input. When the adder overflows, send your data. This gives you a fractional division of the PLL frequency. OutputRate=PLL_Freq*DeltaPhase/2^AdderBits. The more adder bits, the finer the resolution, but the adder has to work at speed also.
