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Honored Contributor
Honored Contributorvalid out and data out problem
Hello. I have builded very simple test design with DSP builder advanced blockset (ModelPrim blocks only) for calculating angle from accelerometer data. It has channel in/out, two convert blocks...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- My block is clocked by 30MHz but signaltap is clocked by 50MHz. Change my block clocking, but forget to change signaltap's reference clock. --- Quote End --- For reliable signaltap reading you should use same clock that samples the data in your logic otherwise you get signaltap timing or phase issues.
