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Altera_Forum's avatar
Altera_Forum
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13 years ago

valid out and data out problem

Hello. I have builded very simple test design with DSP builder advanced blockset (ModelPrim blocks only) for calculating angle from accelerometer data. It has channel in/out, two convert blocks...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Your problem is far from clear.

your signal valid_o seems to have two rates. two clocks in first or second signaltap but one clock in third signaltap. Is that expected.

vout has one clock duration then becomes two clocks??