Using VIP suite for Up-Scaling.

Thank you sir for replying.

But sir in my design i have no external RAM, so i am restricted to use frame buffer MegaCore function.

Can you please let me know, what could be the FIFO depth which can be used in CVI(Clocked video input) and CVO(Clocked video output).

design flow as below:

DVI -------> CVI --------> Scalar ---------> CSC ------------>CR----------->CVO

(1280X1024@60Hz (1920X1080@60Hz

Pclk-108MHz) Clk-148.5MHz)

Here Sir, i used Bridge Clock @148.5MHz.

So sir Is there any way without using frame buffer to solve this clock timing problem, by using only FPGA(cyclone iv gx) inbuilt memory?

Thank you

Keshav