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I am using QSYS on the MAX10. I am interfacing to another board over an LVDS Physical Layer using a UART. The data rate is 80 MHZ. I am planning on oversampling at a clock rate 4x the data rate ie 320 MHz.
How can I do this? Can I do this using the altera_up_avalon_rs232 or altera_avalon_uart
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You are going to have serious problems getting any compiled design to run at 320MHz on the MAX 10 device. This is operating at the very high end of the PLL clock tree generator output (depending on speed grade) and any logic you want to run at 320MHz will likely need to be hand generated and placed to be able to come anywhere close to meeting timing.
I think you need to rethink your communication architecture and not use 4X oversampling but rather some type of DDR clocking protocol.
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