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Yes that would help but I intend to retain the rest of the design to be the same and do not want major changes. When I consulted with Altera they suggested the above quoted solution if I intend to go with the standard PCS. I am waiting for their response meanwhile wanted to know if some one already tried it.
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If you look at the hierarchy in your synthesized design, you will see that the components are named with sv_xxx or xxx_sv, where sv = Stratix V, i.e., the Arria V GZ transceivers match those on the Stratix V. Altera's suggestion implies there is probably an over-ride option for the "allowable range of data rates" rather than actually changing the IP core, since the cores appear to be the same for both of these devices.
Unfortunately I have never heard of that over-ride, sorry.
What 10Gbps interfaces are you working with? I'm trying to get some QSFP+ links working. I can get nice clean eye patterns for internal loopback mode at 10Gbps, but any "real-world" tests have not been very successful. I suspect the hardware I have is not up to the task, i.e., a Texas Instruments TSW14J56 Arria V GZ board with FMC connector and a VadaTech FMC108 FMC-to-QSFP+ with Vitesse redriver PHYs. If your hardware happens to have QSFP+ connectors, or 10Gbps on SMA connectors, I'd be interested in seeing some eye-pattern sweeps created using the Transceiver Toolkit.
Cheers,
Dave
Honored Contributor
